1. Technical Background
The progress of LSI technology is extremely rapid, and the degree of integration is increasing year by year. Taking as an example dynamic random access memory (DRAM), memory capacity has quadrupled in three years. The product development for a 4-megabit DRAM has now been completed, and technical development is now directed to 16-megabit and 64-megabit DRAMs. With the increase in the degree of integration, the dimension of a unit element is minimized, and the minimum dimension is rapidly decreasing from 1 .mu.m to the order of submicron. Various devices and IC's are basically composed of a laminated structure of various types of thin film. For example, the main portion of a MOS transistor is composed of a 3-layer structure comprising electrode material, insulating thin film, and semiconductor substrate. The capacitor used for a memory cell of a DRAM has a 3-layer structure with a high dielectric thin film sandwiched by upper and lower electrode materials. A non-volatile memory element has a 5-layer structure composed of semiconductor substrate, insulating thin film, electrode material, insulating thin film, and electrode material. Thus, the thin film laminated structure dominates the most important characteristics of the device. Because the thickness of these thin films is increasingly becoming thinner with the miniaturization of the device, the characteristics of these thin films are the important factor to determine the characteristics, yield and reliability of the LSI. Therefore, the key point for the realization of ultra-high integration is the technique to form high quality thin films and to produce the laminated structure of thin films with high reliability. Further, this process requires low temperatures instead of the high temperatures of 900.degree.-1000.degree. C. as used at present. For example to produce a capacitor structure using aluminum as a lower electrode, the temperature utilized to form an insulating film and an electrode on it must be lower than the melting point of aluminum (about 630.degree. C.) for instance, 500.degree.-550.degree. C. or less--or more preferably, 400.degree. C. or less. For accurate control of N-type or P-type impurities, it is necessary to reduce the process temperature to 700.degree. C. or less.
In the following, description will be given of the method to produce a conventional type thin film laminated structure, taking as an example the manufacturing process of a DRAM memory cell.
FIG. 7 is a schematic drawing showing the cross sectional structure of a memory capacitor unit 701 of a DRAM memory cell as formed by the conventional technique. To produce this structure, field oxide film 703 is formed on silicon substrate 702, and the surface of silicon substrate 702 of memory capacitor forming portion 701 is exposed. Then, SiO.sub.2 film 704 of about 100 .ANG. is formed by thermal oxidation at 900.degree. C. (This SiO.sub.2 film acts as a capacitor insulating film.) Thereafter, polycrystal silicon thin film 705 is deposited by a CVD method, and the memory capacitor is produced by patterning it into the predetermined shape. In this process, after the surface of silicon substrate 702 is exposed by etching with dilute HF solution, the wafer is placed into a thermal oxidation furnace to grow the oxide film. After the wafer is taken out of the furnace, it is placed into a CVD apparatus and polycrystal silicon film 705 is deposited, and this is processed to form the predetermined pattern. As a result, the interface of each thin film comes into contact with atmospheric air because each thin film which composes the laminated structure is formed in a separate apparatus in the normal process. For this reason, the interfaces are contaminated by adsorption of contaminants in the atmospheric air, and this results in instability and variation of the isolation voltage or other characteristics of the thin film oxide film. An oxide film of 100 .ANG. thickness is the insulating film to be used for a 1-megabit DRAM. For a 4-megabit or 16-megabit DRAM, it is necessary to have a thin film of 50 .ANG. or thinner, and the problem of interface contamination is an important and serious issue concerning the decrease of isolation voltage or the reliability of the thin film oxide film. In some cases, a silicon nitride film (Si.sub.3 N.sub.4) thin film having a higher dielectric constant than the thermal oxide film of Si (SiO.sub.2) is used as the capacitor insulating film 704 of DRAM. Because it is very difficult to form Si.sub.3 N.sub.4 film through direct nitriding of silicon Si.sub.3 N.sub.4 film deposited by a LPCVD method is used. Normally, such thin film formed by depositing has poor characteristics in the interface with silicon and there are more defects such as pinholes. Accordingly, after the silicon surface is processed by thermal oxidation, the characteristics of the interface with Si are improved by depositing a Si.sub.3 N.sub.4 film, and any pinholes are filled up by thermal oxidation after the Si.sub.3 N.sub.4 film is deposited.
In such a process, the final capacitor structure is a 5-layer laminated structure composed of Si, SiO.sub.2, Si.sub.3 N.sub.4, SiO.sub.2 and poly-Si (polycrystal silicon), and this means that there are four interfaces to be exposed to atmospheric air, and it is very difficult to prevent contamination.
FIG. 8 shows another example of a thin film laminated structure formed by conventional techniques, and it represents the structure of the connection between N.sup.+ area 802 formed in P-type semiconductor substrate 801 and metal wiring 803. To obtain this structure, N.sup.+ area 802 is formed in wafer (Si substrate) 801, and SiO.sub.2 film 804 is formed over the entire surface. Then, an opening 805 is provided in the predetermined portion of SiO.sub.2 film 804. Next, Al-Si alloy thin film is formed over the entire surface to a thickness of about 0.8-1 .mu.m, and it is fabricated into the predetermined circuit pattern by a photolithography process. One of the problems with this structure is the electrical contact between metal wiring 803 and N.sup.+ area 802. By conventional techniques, N.sup.+ area surface 806 is exposed to atmospheric air before the Al-Si thin film is formed after the contact hole 805 is opened, and a very thin natural oxide film is often formed on the surface or gas molecules in the atmospheric air are adsorbed on the surface of N.sup.+ surface 806, and this results in poor contact whereby the contact resistance is increased. For this reason, it has been attempted to increase the temperature of the wafer to 400.degree.-450.degree. C. after metal wiring 803 was formed, and the natural oxide film or adsorbed objects were absorbed by the metal wiring 803 in order to attain good metal-semiconductor contact. Specifically, to attain metal-semiconductor contact by the conventional techniques, it was indispensable to perform heat treatment at 400.degree.-450.degree. C. In such a heat treatment process, when the wafer temperature is decreased from a high temperature of 400.degree.-450.degree. C. to normal temperature, Si in Al-Si thin film 803 is deposited at the interface 806, and this resulted in wide variations of contact resistance. Particularly, in a contact opening of 1 .mu.m or less, such Si deposits cover the entire surface of the contact (interface 806) and cause problems such as poor contact. On the other hand, if pure aluminum metal is used as metal wiring 803 instead of an alloy in order to prevent Si deposition, Al is melted into the Si when the temperature is raised to 400.degree.-450.degree. C. It penetrates N.sup.+ -layer 802, reaches the P-type semiconductor substrate 801 and destroys the PN-junction. Thus, it is very difficult by conventional techniques to have good electrical contact between the metal wiring and the Si substrate.
To realize ultra-high integration in the future, it is very important to develop a technique to produce the laminated structure of very thin films at low temperature and with no possibility to induce contamination at the interface.
To attain such a result, the present invention provides a reduced pressure surface treatment apparatus and a reduced pressure surface treatment method suitable for the manufacture of ultra-high density integrated circuits.
2. Disclosure of the Invention
The present invention offers a reduced pressure surface treatment apparatus, comprising a vacuum chamber, an exhaust unit connected thereto and a gas supply unit, characterized in that it is provided with a holder to hold the specimen, means to bombard the specimen with ions without depositing a thin film on the surface of said specimen, and means to control the kinetic energy of said ions to a small value.
The reduced pressure surface treatment method according to this invention is characterized in that substances adsorbed on a wafer surface or the natural oxide film layer are removed by impinging ions on the wafer surface under a vacuum condition.